This invention relates to a method for laying out an integrated circuit chip including intermixed fixed size and shape rectangular macrocells together with amorphous clusters of standard cells.
Modern integrated circuit technology is widely used for communications and control. Because of the advantages of reliability and operating speed, the complexity of integrated circuit chips has increased with time, notwithstanding the disadvantages of lower yields occasioned by such complex chips. At the current state of technology, up to one million transistors may be used on a single large-scale integrated circuit.
While such large integrated circuits are advantageous, the initial layout of such complex devices, and of the interconnections between the transistors presents problems in the length of time required to accomplish the layout of the interconnections, the total man-hours required, and in the high skill required of the layout personnel. Furthermore, human layout is subject to the problem of errors, and also is undesirably dependent upon human intuition, rather than upon rote evaluation of all possible permutations of the layout. Thus, layout by humans may not be optimum in terms of the chip size and operating speed of the resulting integrated circuit. The larger chip size resulting from human layout, in turn, results in lower yields during the manufacture of the integrated circuit, which increases the cost.
As a result of the limitations of human layout, it has become common to lay out the integrated circuits including the transistors and their interconnections by means of computer-aided design. These computerized layout systems accept as inputs an interconnection list between the logic elements. In this context, logic elements are relatively primitive electrical circuit such as AND gates, OR gates, and the like. Such logic elements are often standard cells having a fixed dimension and a variable dimension to aid in their placement. Other inputs to the computer layout program include the physical sizes associated with the standard cells, and the locations of the connection points (pins) around the peripheries of the standard cells.
Various methods have been devised for operating on this information to produce the desired layout. One method is described in U.S. Pat. No. 4,593,363 issued June 3, 1986 to Burstein et al. This method operates only with standard cells. This has the disadvantage that LSI layouts including macrocells cannot be conveniently handled except by the intervention of human layout experts. Macrocells, on the other hand, are relatively sophisticated circuits such as memories or multipliers, digital filters and the like, which have fixed dimensions, often because they were laid out by hand. In general, the structure of macrocells is regular. Furthermore, Burstein et al. optimizes the layout for operating speed and not for chip area. Another system is described in U.S. Pat. No. 4,577,276 issued March 18, 1986 to Dunlop et al., which has the same disadvantages as Burstein et al. Copending U.S. allowed application Ser. No. 886,936, filed July 21, 1986, by Noto et al., entitled "Logic Cell Placement Method in Computer-Aided-Customization of Universal Arrays and Resulting Integrated Circuit," is a logic cell placement method for gate arrays, which are fixed structures. These logic arrays are fixed-size chips laid out with an inflexible array of logic elements, which are interconnected in various ways by variations of the last masking level.
The circuits normally found in the form of macrocells are used in many systems, and it is very desirable to be able to include them in a large scale integrated (LSI) circuit. It would be advantageous to have an automated chip layout system which simultaneously optimizes chip speed and minimizes area, and which handles intermixed standard cells and macrocells.